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2 adc/8 dac with pll, 192 khz, 24-bit codec adau1328 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features pll generated or direct master clock low emi design 108 db dac/107 db adc dynamic range and snr ?94 db thd + n single 3.3 v supply tolerance for 5 v logic inputs supports 24 bits and 8 khz to 192 khz sample rates differential adc input single-ended dac output log volume control with autoramp function spi? controllable for flexibility software controllable clickless mute software power-down right justified, left justified, i 2 s and tdm modes master and slave modes up to 16-channel in/out 48-lead lqfp applications home theater systems set-top boxes digital audio effects processors general description the adau1328 is a high performance, single-chip codec that provides two analog-to-digital converters (adcs) with differential input and eight digital-to-analog converters (dacs) with single-ended output using the analog devices, inc. patented multibit sigma-delta (-) architecture. an spi port is included, allowing a microcontroller to adjust volume and many other parameters. the adau1328 operates from 3.3 v digital and analog supplies. the adau1328 is available in a 48-lead (single-ended output) lqfp. other members of this family include a differential dac output and i 2 c? control port version. the adau1328 is designed for low emi. this consideration is apparent in both the system and circuit design architectures. by using the on-board pll to derive the master clock from the lr clock or from an external crystal, the adau1328 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. the digital-to-analog and analog-to-digital converters are designed using the latest adi continuous time architectures to further minimize emi. by using 3.3 v supplies, power consumption is minimized, further reducing emissions. functional block diagram dec filter 48/96/ 192khz serial data port digital audio input/output precision voltage reference timing management and control (clock and pll) control port spi/i 2 c control data input/output 12.488mhz 6.144mhz adau1328 adc adc dac dac dac dac dac dac dac dac digital filter and volume control sdata out sdata in clocks 06102-001 figure 1.
adau1328 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 test conditions ............................................................................. 3 analog performance specifications ........................................... 3 crystal oscillator specifications ................................................. 4 digital input/output specifications ........................................... 4 power supply specifications ........................................................ 5 digital filters ................................................................................. 6 timing specifications .................................................................. 6 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 13 analog-to-digital converters (adcs) .................................... 13 digital-to-analog converters (dacs) .................................... 13 clock signals ............................................................................... 13 reset and power-down ............................................................. 14 serial control port ..................................................................... 14 power supply and voltage reference ....................................... 15 serial data portsdata format ............................................... 15 time-division multiplexed (tdm) modes ............................ 15 daisy-chain mode ..................................................................... 19 control registers ............................................................................ 24 definitions ................................................................................... 24 pll and clock control registers ............................................. 24 dac control registers .............................................................. 25 adc control registers .............................................................. 27 additional modes ....................................................................... 29 application circuits ....................................................................... 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision history 6/06revision 0: initial version
adau1328 rev. 0 | page 3 of 32 specifications test conditions performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specific ations. supply voltages (avdd, dvdd) 3.3 v temperature range 1 as specified in table 1 master clock 12.288 mhz (48 khz f s , 256 f s mode) input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance (digital output) 20 pf load current (digital output) 1 ma or 1.5 k to ? dvdd supply input voltage hi 2.0 v input voltage lo 0.8 v 1 functionally guaranteed at ?40c to +85c case temperature. analog performance specifications specifications guaranteed at 25c (ambient). table 1. parameter conditions min typ max unit analog-to-digital converters adc resolution all adcs 24 bits dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 98 102 db with a-weighted filter (rms) 100 105 db total harmonic distortion + noise ?1 dbfs ?96 ?87 db gain error ?10 +10 % interchannel gain mismatch ?0.25 +0.25 db offset error ?10 0 +10 mv gain drift 100 ppm/c interchannel isolation ?110 db cmrr 100 mv rms, 1 khz 55 db 100 mv rms, 20 khz 55 db input resistance 14 k input capacitance 10 pf input common-mode bias voltage 1.5 v digital-to-analog converters dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 98 104 db with a-weighted filter (rms) 100 106 db with a-weighted filter (avg) 108 db total harmonic distortion + noise 0 dbfs single-ended version two channels running ?92 db eight channels running ?86 ?75 db full-scale output voltage 0.88 (2.48) v rms (v p-p) gain error ?10 +10 % interchannel gain mismatch ?0.2 +0.2 db offset error ?16 ?4 16 mv gain drift ?30 30 ppm/c interchannel isolation 100 db
adau1328 rev. 0 | page 4 of 32 parameter conditions min typ max unit interchannel phase deviation 0 degrees volume control step 0.375 db volume control range 95 db de-emphasis gain error 0.6 db output resistance at each pin 100 reference internal reference voltage filtr pin 1.50 v external reference voltage filtr pin 1.32 1.50 1.68 v common-mode reference output cm pin 1.50 v crystal oscillator specifications table 2. parameter min typ max unit transconductance 3.5 mmhos digital input/output specifications ?40c < t a < +85c, dvdd = 3.3 v 10%. table 3. parameter conditions/comments min typ max unit input voltage hi (v ih ) 2.0 v input voltage hi (v ih ) mclki pin 2.2 v input voltage lo (v il ) 0.8 v input leakage i ih @ v ih = 2.4 v 10 a i il @ v il = 0.8 v 10 a high level output voltage (v oh ) i oh = 1 ma dvdd ? 0.60 v low level output voltage (v ol ) i ol = 1 ma 0.4 v input capacitance 5 pf
adau1328 rev. 0 | page 5 of 32 power supply specifications table 4. parameter conditions/comments min typ max unit supplies voltage dvdd 3.0 3.3 3.6 v avdd 3.0 3.3 3.6 v digital current mclk = 256 f s normal operation f s = 48 khz 56 ma f s = 96 khz 65 ma f s = 192 khz 95 ma power-down f s = 48 khz to 192 khz 2.0 ma analog current normal operation 74 ma power-down 23 ma dissipation operation mclk = 256 f s , 48 khz all supplies 429 mw digital supply 185 mw analog supply 244 mw power-down, all supplies 83 mw power supply rejection ratio signal at analog supply pins 1 khz, 200 mv p-p 50 db 20 khz, 200 mv p-p 50 db
adau1328 rev. 0 | page 6 of 32 digital filters table 5. parameter mode factor min typ max unit adc decimation filter all modes, typ @ 48 khz pass band 0.4375 f s 21 khz pass-band ripple 0.015 db transition band 0.5 f s 24 khz stop band 0.5625 f s 27 khz stop-band attenuation 79 db group delay 22.9844/f s 479 s dac interpolation filter pass band 48 khz mode, typ @ 48 khz 0.4535 f s 22 khz 96 khz mode, typ @ 96 khz 0.3646 f s 35 khz 192 khz mode, typ @ 192 khz 0.3646 f s 70 khz pass-band ripple 48 khz mode, typ @ 48 khz 0.01 db 96 khz mode, typ @ 96 khz 0.05 db 192 khz mode, typ @ 192 khz 0.1 db transition band 48 khz mode, typ @ 48 khz 0.5 f s 24 khz 96 khz mode, typ @ 96 khz 0.5 f s 48 khz 192 khz mode, typ @ 192 khz 0.5 f s 96 khz stop band 48 khz mode, typ @ 48 khz 0.5465 f s 26 khz 96 khz mode, typ @ 96 khz 0.6354 f s 61 khz 192 khz mode, typ @ 192 khz 0.6354 f s 122 khz stop-band attenuation 48 khz mode, typ @ 48 khz 70 db 96 khz mode, typ @ 96 khz 70 db 192 khz mode, typ @ 192 khz 70 db group delay 48 khz mode, typ @ 48 khz 25/f s 521 s 96 khz mode, typ @ 96 khz 11/f s 115 s 192 khz mode, typ @ 192 khz 8/f s 42 s timing specifications ?40c < t a < +85c, dvdd = 3.3 v 10%. table 6. parameter condition comments min max unit input master clock (mclk) and reset t mh mclk duty cycle dac/adc clock source = pll clock @ 256 f s , 384 f s , 512 f s , 768 f s 40 60 % t mh dac/adc clock source = direct mclk @ 512 f s (bypass on-chip pll) 40 60 % f mclk mclk frequency pll mode, 256 f s reference 6.9 13.8 mhz f mclk direct 512 f s mode 27.6 mhz t pdr rst low 15 ns t pdrr rst recovery reset to active output 4096 t mclk pll lock time mclk and lrclk input 10 ms 256 f s vco clock, output duty cycle mclko pin 40 60 %
adau1328 rev. 0 | page 7 of 32 parameter condition comments min max unit spi port see figure 11 t cch cclk high 35 ns t ccl cclk low 35 ns f cclk cclk frequency f cclk = 1/t ccp , only t ccp shown in figure 11 10 mhz t cds cdata setup to cclk rising 10 ns t cdh cdata hold from cclk rising 10 ns t cls clatch setup to cclk rising 10 ns t clh clatch hold from cclk falling 10 ns t clhigh clatch high not shown in figure 11 10 ns t coe cout enable from cclk falling 30 ns t cod cout delay from cclk falling 30 ns t coh cout hold from cclk falling, not shown in figure 11 30 ns t cots cout tri-state from cclk falling 30 ns dac serial port see figure 24 t dbh dbclk high slave mode 10 ns t dbl dbclk low slave mode 10 ns t dls dlrclk setup to dbclk rising, slave mode 10 ns t dlh dlrclk hold from dbclk rising, slave mode 5 ns t dls dlrclk skew from dbclk falling, master mode ?8 +8 ns t dds dsdata setup to dbclk rising 10 ns t ddh dsdata hold from dbclk rising 5 ns adc serial port see figure 25 t abh abclk high slave mode 10 ns t abl abclk low slave mode 10 ns t als alrclk setup to abclk rising, slave mode 10 ns t alh alrclk hold from abclk rising, slave mode 5 ns t als alrclk skew from abclk falling, master mode ?8 +8 ns t abdd asdata delay from abclk falling 18 ns auxiliary interface t axds aauxdata setup to auxbclk rising 10 ns t axdh aauxdata hold from auxbclk rising 5 ns t dxdd dauxdata delay from auxbclk falling 18 ns t xbh auxbclk high 10 ns t xbl auxbclk low 10 ns t dls auxlrclk setup to auxbclk rising 10 ns t dlh auxlrclk hold from auxbclk rising 5 ns
adau1328 rev. 0 | page 8 of 32 absolute maximum ratings table 7. parameter rating analog (avdd) ?0.3 v to +3.6 v digital (dvdd) ?0.3 v to +3.6 v input current (except supply pins) 20 ma analog input voltage (signal pins) C0.3 v to avdd + 0.3 v digital input voltage (signal pins) ?0.3 v to dvdd + 0.3 v operating temperature range (case) ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja represents thermal resistance, junction-to-ambient; jc represents the thermal resistance, junction-to-case. all characteristics are for a 4-layer board. table 8. thermal resistance package type ja jc unit 48-lead lqfp 50.1 17 c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adau1328 rev. 0 | page 9 of 32 pin configuration and fu nction descriptions avdd 48 lf 47 adc2rn 46 adc2rp 45 adc2ln 44 adc2lp 43 adc1rn 42 adc1rp 41 adc1ln 40 adc1lp 39 cm 38 avdd 37 dvdd 13 dsdata3 14 dsdata2 15 dsdata1 16 dbclk 17 dlrclk 18 asdata2 19 asdata1 20 abclk 21 alrclk 22 cin/adr0 23 cout/sd a 24 agnd 1 mclki/xi 2 mclko/xo 3 agnd 4 avdd 5 ol3 6 or3 7 ol4 8 or4 9 pd/rst 10 dsdata4 11 dgnd 12 agnd 36 filtr 35 agnd 34 avdd 33 agnd 32 or2 31 ol2 30 or1 29 ol1 28 clatch/adr1 27 cclk/scl 26 dgnd 25 adau1328 top view (not to scale) single-ended output 06102-020 figure 2. pin configuration table 9. pin function description pin o. in/ut mnemonic description 1 i agnd analog ground. 2 i mclki/xi master clock input/crystal oscillator input. 3 o mclko/xo master clock output/crystal oscillator output. 4 i agnd analog ground. 5 i avdd analog power supply. connect to analog 3.3 v supply. 6 o ol3 dac 3 left output. 7 o or3 dac 3 right output. 8 o ol4 dac 4 left output. 9 o or4 dac 4 right output. 10 i pd / rst power-down reset (active low). 11 i/o dsdata4 dac input 4 (input to dac 4 l and r)/dac tdm data out 2/aux adc 1 data in. 12 i dgnd digital ground. 13 i dvdd digital power supply. connect to digital 3.3 v supply. 14 i/o dsdata3 dac input 3 (input to dac 3 l and r)/dac tdm data in 2/aux dac 2 data output. 15 i/o dsdata2 dac input 2 (input to dac 2 l and r)/dac tdm data out 1/aux adc 1 data in. 16 i dsdata1 dac input 1 (input to dac 1 l and r)/dac tdm data in 1/aux adc 2 data in. 17 i/o dbclk bit clock for dacs. 18 i/o dlrclk lr clock for dacs. 19 i/o asdata2 adc serial data output 2 (adc 2 l an d r)/adc tdm data input/aux dac 1 data output. 20 o asdata1 adc serial data output 1 (a dc 1 l and r)/adc tdm data output. 21 i/o abclk bit clock for adcs. 22 i/o alrclk lr clock for adcs. 23 i cin/adr0 control data input (spi). 24 i/o cout/sda control data output (spi). 25 i dgnd digital ground.
adau1328 rev. 0 | page 10 of 32 pin no. in/out mnemonic description 26 i cclk/scl control clock input (spi). 27 i clatch /adr1 latch input for control data (spi). 28 o ol1 dac 1 left output. 29 o or1 dac 1 right output. 30 o ol2 dac 2 left output. 31 o or2 dac 2 right output. 32 i agnd analog ground. 33 i avdd analog power supply. connect to analog 3.3 v supply. 34 i agnd analog ground. 35 o filtr voltage reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 36 i agnd analog ground. 37 i avdd analog power supply. connect to analog 3.3 v supply. 38 o cm common-mode reference filter capacitor connection. bypass with 47 f||100 nf to agnd. 39 i adc1lp adc1 left positive input. 40 i adc1ln adc1 left negative input. 41 i adc1rp adc1 right positive input. 42 i adc1rn adc1 right negative input. 43 i adc2lp adc2 left positive input. 44 i adc2ln adc2 left negative input. 45 i adc2rp adc2 right positive input. 46 i adc2rn adc2 right negative input. 47 o lf pll loop filter. return to avdd. 48 i avdd analog power supply. connect to analog 3.3 v supply.
adau1328 rev. 0 | page 11 of 32 typical performance characteristics 0.10 0.08 0.06 0.04 0.02 0 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 18000 16000 14000 12000 10000 8000 6000 4000 2000 magnitude (db) frequency (hz) 06102-002 figure 3. adc pass-band filter response, 48 khz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 40000 5000 10000 15000 20000 25000 30000 35000 magnitude (db) frequency (hz) 06102-003 figure 4. adc stop-band filter response, 48 khz 0.06 0.04 0.02 ?0.06 ?0.04 ?0.02 0 02 4 06102-004 8 16 8 magnitude (db) frequency (khz) figure 5. dac pass-band filter response, 48 khz 0 ?150 ?100 ?50 04 12 24 36 magnitude (db) frequency (khz) 06102-005 figure 6. dac stop-band filter response, 48 khz 0.10 ?0.10 ?0.05 0 0.05 09 72 48 24 magnitude (db) frequency (khz) 6 06102-006 figure 7. dac pass-band filter response, 96 khz 0 ?150 ?100 ?50 09 6 24 48 72 magnitude (db) frequency (khz) 06102-007 figure 8. dac stop-band filter response, 96 khz
adau1328 rev. 0 | page 12 of 32 4 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 06 81 63 2 magnitude (db) frequency (khz) 06102-008 ?10 ?8 ?6 ?4 ?2 0 48 96 64 80 magnitude (db) frequency (khz) 06102-009 figure 10. dac stop-band filter response, 192 khz figure 9. dac pass-band filter response, 192 khz
adau1328 rev. 0 | page 13 of 32 theory of operation analog-to-digital converters (adcs) there are two adc channels in the adau1328 configured as two stereo pairs with differential inputs. the adcs can operate at a nominal sample rate of 48 khz, 96 khz, or 192 khz. the adcs include on-board digital antialiasing filters with 79 db stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 khz, 96 khz, and 192 khz modes). digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame (alrclk) and bit (abclk) clock. alternatively, one of the tdm modes can be used to access up to 16 channels on a single tdm data line. the adcs must be driven from a differential signal source for best performance. the input pins of the adcs connect to internal switched capacitors. to isolate the external driving op amp from the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series connected, external, 100 resistor together with a 1 nf capacitor connected from each input to ground. this capacitor must be of high quality, for example, ceramic npo or polypropylene film. the differential inputs have a nominal common-mode voltage of 1.5 v. the voltage at the common-mode reference pin (cm) can be used to bias external op amps to buffer the input signals (see the power supply and voltage reference section). the inputs can also be ac-coupled and do not need an external dc bias to cm. a digital high-pass filter can be switched in line with the adcs under serial control to remove residual dc offsets. it has a 1.4 hz, 6 db per octave cutoff at a 48 khz sample rate. the cutoff frequency scales directly with sample frequency. digital-to-analog converters (dacs) the adau1328 dac channels are arranged as single-ended, four stereo pairs giving eight analog outputs for minimum external components. the dacs include on-board digital reconstruction filters with 70 db stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 khz or 96 khz modes) or 2 (192 khz mode). each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 db. digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (dlrclk) and bit (dbclk) clock. alternatively, one of the tdm modes can be used to access up to 16 channels on a single tdm data line. each output pin has a nominal common-mode dc level of 1.5 v and swings 1.27 v for a 0 dbfs digital input signal. a single op amp, third-order, external, low-pass filter is recommended to remove high frequency noise present on the output pins. the use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. the voltage at cm, the common-mode reference pin, can be used to bias the external op amps that buffer the output signals (see the power supply and voltage reference section). clock signals the on-chip phase locked loop (pll) can be selected to reference the input sample rate from either of the lrclk pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 khz mode from the mclki pin. the default at power-up is 256 f s from mclki. in 96 khz mode, the master clock fre- quency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. in 192 khz mode, the actual multiplication rate is divided by 4. for example, if a device in the adau1328 family is programmed in 256 f s mode, the frequency of the master clock input is 256 48 khz = 12.288 mhz. if the adau1328 is then switched to 96 khz operation (by writing to the spi or i 2 c port), the frequency of the master clock should remain at 12.288 mhz, which is now 128 f s . in 192 khz mode, this becomes 64 f s . the internal clock for the adcs is 256 f s for all clock modes. the internal clock for the dacs varies by mode: 512 f s (48 khz mode), 256 f s (96 khz mode), or 128 f s (192 khz mode). by default, the on-board pll generates this internal master clock from an external clock. a direct 512 f s (referenced to 48 khz mode) master clock can be used for either the adcs or dacs if selected in pll and clock control 1 register. note that it is not possible to use a direct clock for the adcs set to the 192 khz mode. it is required that the on-chip pll be used in this mode. the pll can be powered down in pll and clock control 0 register. to ensure reliable locking when changing pll modes, or if the reference clock is unstable at power-on, power down the pll and then power it back up when the reference clock has stabilized. the internal mclk can be disabled in pll and clock control 0 register to reduce power dissipation when the adau1328 is idle. the clock should be stable before it is enabled. unless a standalone mode is selected (see the serial control port section), the clock is disabled by reset and must be enabled by writing to the spi or i 2 c port for normal operation.
adau1328 rev. 0 | page 14 of 32 to maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms time interval error (tie). even at these levels, extra noise or tones can appear in the dac outputs if the jitter spectrum contains large spectral peaks. if the internal pll is not being used, it is highly recommended that an independent crystal oscillator generate the master clock. in addition, it is especially important that the clock signal not be passed through an fpga, cpld, or other large digital chip (such as a dsp) before being applied to the adau1328. in most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. when the pll is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. reset and power-down reset sets all the control registers to their default settings. to avoid pops, reset does not power down the analog outputs. after reset is deasserted, and the pll acquires lock condition, an initialization routine runs inside the adau1328. this initialization lasts for approximately 256 mclks. the power-down bits in the pll and clock control 0, dac control 1, and adc control 1 registers power down the respective sections. all other register settings are retained. the reset pin should be pulled low by an external resistor to guarantee proper startup. serial control port the adau1328 has an spi control port that permits programming and reading back of the internal control registers for the adcs, dacs, and clock system. there is also a stand- alone mode available for operation without serial control that is configured at reset using the serial control pins. all registers are set to default, except the internal mclk enable is set to 1 and adc bclk and lrclk master/slave is set by cout/sda. refer to table 10 for details. it is recommended to use a weak pull-up resistor on clatch in applications that have a microcontroller. this pull-up resistor ensures that the adau1328 recognizes the presence of a microcontroller. the spi control port of the adau1328 is a 4-wire serial control port. the format is similar to the motorola spi format except the input data-word is 24 bits wide. the serial bit clock and latch can be completely asynchronous to the sample rate of the adcs and dacs. figure 11 shows the format of the spi signal. the first byte is a global address with a read/write bit. for the adau1328, the address is 0x04, shifted left 1 bit due to the r/ w bit. the second byte is the adau1328 register address and the third byte is the data. table 10. standalone mode selection adc clocks cin/adr0 cout/sda cclk/scl clatch /adr1 slave 0 0 0 0 master 0 1 0 0 d0 d0 d8 d8 d22 d23 d9 d9 c latch cclk cin cout t cch t ccl t cds t cdh t cls t ccp t clh t cots t cod t coe 06102-010 figure 11. format of spi signal
adau1328 rev. 0 | page 15 of 32 power supply and voltage reference the adau1328 is designed for 3.3 v supplies. separate power supply pins are provided for the analog and digital sections. these pins should be bypassed with 100 nf ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same pc board as the codec. for critical applications, improved performance is obtained with separate supplies for the analog and digital sections. if this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. it is important that the analog supply be as clean as possible. all digital inputs are compatible with ttl and cmos levels. all outputs are driven from the 3.3 v dvdd supply and are compatible with ttl and 3.3 v cmos levels. the adc and dac internal voltage reference (vref) is brought out on filtr and should be bypassed as close as possible to the chip, with a parallel combination of 10 f and 100 nf. any external current drawn should be limited to less than 50 a. the internal reference can be disabled in pll and clock control 1 register, and filtr can be driven from an external source. this can be used to scale the dac output to the clipping level of a power amplifier based on its power supply voltage. the adc input gain varies by the inverse ratio. the total gain from adc input to dac output remains constant. the cm pin is the internal common-mode reference. it should be bypassed as close as possible to the chip, with a parallel combination of 47 f and 100 nf. this voltage can be used to bias external op amps to the common-mode voltage of the input and output signal pins. the output current should be limited to less than 0.5 ma source and 2 ma sink. serial data portsdata format the eight dac channels use a common serial bit clock (dbclk) and a common left-right framing clock (dlrclk) in the serial data port. the four adc channels use a common serial bit clock (abclk) and left-right framing clock (alrclk) in the serial data port. the clock signals are all synchronous with the sample rate. the normal stereo serial modes are shown in figure 23 . the adc and dac serial data modes default to i 2 s. the ports can also be programmed for left justified, right justified, and tdm modes. the word width is 24 bits by default and can be programmed for 16 or 20 bits. the dac serial formats are programmable according to dac control 0 register. the polarity of the dbclk and dlrclk is programmable according to dac control 1 register. the adc serial formats and serial clock polarity are programmable according to adc control 1 register. both dac and adc serial ports are programmable to become the bus masters according to dac control 1 register and control 2 register. by default, both adc and dac serial ports are in the slave mode. time-division multiplexed (tdm) modes the adau1328 serial ports also have several different tdm serial data modes. the first and most commonly used configurations are shown in figure 12 and figure 13 . in figure 12 , the adc serial port outputs one data stream consisting of four on-chip adcs followed by four unused slots. in figure 13 , the eight on-chip dac data slots are packed into one tdm stream. in this mode, both dbclk and abclk are 256 f s . the i/o pins of the serial ports are defined according to the serial mode selected. for a detailed description of the function of each pin in tdm and aux modes, see table 11 . the adau1328 allows systems with more than eight dac channels to be easily configured by the use of an auxiliary serial data port. the dac tdm-aux mode is shown in figure 14 . in this mode, the aux channels are the last four slots of the tdm data stream. these slots are extracted and output to the aux serial port. it should be noted that due to the high dbclk frequency, this mode is available only in the 48 khz/44.1 khz/32 khz sample rate. the adau1328 also allows system configurations with more than four adc channels, as shown in figure 15 and figure 16 , which show using 8 adcs and 16 adcs, respectively. again, due to the high abclk frequency, this mode is available only in the 48 khz/44.1 kh z/32 khz sample rate. combining the aux dac and adc modes results in a system configuration of 8 adcs and 12 dacs. the system, then, con- sists of two external stereo adcs, two external stereo dacs, and one adau1328. this mode is shown in figure 17 (combined aux dac and adc modes). slot 1 left 1 slot 2 right 1 slot 3 left 2 slot 4 right 2 msb msb?1 msb?2 data bclk lrclk slot 5 slot 6 slot 7 slot 8 lrclk bclk data 256 bclks 32 bclks 06102-016 figure 12. adc tdm (8-channel i 2 s mode) slot 1 left 1 slot 2 right 1 slot 3 left 2 slot 4 right 2 msb msb?1 msb?2 data bclk lrclk slot 5 left 3 slot 6 right 3 slot 7 left 4 slot 8 right 4 lrclk bclk data 256 bclks 32 bclk 06102-017 figure 13. dac tdm (8-channel i 2 s mode)
adau1328 rev. 0 | page 16 of 32 table 11. pin function changes in tdm and aux modes mnemonic stereo modes tdm modes aux modes asdata1 adc1 data out adc tdm data out tdm data out asdata2 adc2 data out adc tdm data in aux data out 1 (to external dac 1) dsdata1 dac1 data in dac tdm data in tdm data in dsdata2 dac2 data in dac tdm data out aux data in 1 (from external adc 1) dsdata3 dac3 data in dac tdm data in 2 (dual- line mode) aux data in 2 (from external adc 2) dsdata4 dac4 data in dac tdm data out 2 (dual- line mode) aux data out 2 (to external dac 2) alrclk adc lrclk in/out adc tdm frame sync in/out tdm frame sync in/out abclk adc bclk in/out adc tdm bclk in/out tdm bclk in/out dlrclk dac lrclk in/out dac tdm frame sync in/out aux lrclk in/out dbclk dac bclk in/out dac tdm bclk in/out aux bclk in/out left right msb msb msb msb alrclk abclk dsdata1 (tdm_in) dlrclk (aux port) dbclk (aux port) asdata2 ( aux1_out) dsdata4 ( aux2_out) msb empty empty empty empty dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 aux l1 aux r1 aux l2 aux r2 8-on-chip dac channels auxiliary dac channels will appear at aux dac ports unused slots 32 bits 0 6102-051 figure 14. 16-channel dac tdm-aux mode
adau1328 rev. 0 | page 17 of 32 alrclk abclk dsdata1 (tdm_in) asdata1 (tdm_out) dlrclk (aux port) dbclk (aux port) dsdata2 (aux1_in) dsdata3 (aux2_in) dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 adc l1 adc r1 adc l2 adc r2 aux l1 aux r1 aux l2 aux r2 8-on-chip dac channels 4-on-chip adc channels 4-aux adc channels 32 bits left right msb msb msb msb msb 0 6102-050 figure 15. 8-channel aux adc mode left right msb msb msb msb dlrclk (aux port) dbclk (aux port) dsdata2 (aux1_in) dsdata3 (aux2_in) alrclk abclk asdata1 (tdm_out) msb adc l1 adc r1 adc l2 adc r2 aux l1 aux r1 aux l2 aux r2 unused unused unused unused unused unused unused unused 4 on-chip adc channels auxiliary adc channels unused slots 32 bits 06102-052 figure 16. 16-channel aux adc mode
adau1328 rev. 0 | page 18 of 32 left right dlrclk (aux port) dbclk (aux port) msb msb dsdata2 (aux1_in) msb msb dsdata3 (aux2_in) msb msb asdata2 ( aux1_out) msb msb dsdata4 ( aux2_out) alrclk abclk dsdata1 (tdm_in) empty empty empty empty dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 aux l1 aux r1 aux l2 aux r2 8 on-chip dac channels auxiliary dac channels appear at aux dac ports unused slots asdata1 (tdm_out) adc l1 adc r1 adc l2 adc r2 aux l1 aux r1 aux l2 aux r2 unused unused unused unused unused unused unused unused 4 on-chip adc channels auxiliary adc channels unused slots 0 6102-053 figure 17. combined aux dac and adc mode
adau1328 rev. 0 | page 19 of 32 daisy-chain mode the adau1328 also allows a daisy-chain configuration to expand the system to 8 adcs and 16 dacs (see figure 18 ). in this mode, the dbclk frequency is 512 f s . the first eight slots of the dac tdm data stream belong to the first adau1328 in the chain and the last eight slots belong to the second adau1328. the second adau1328 is the device attached to the dsp tdm port. to accommodate 16 channels at a 96 khz sample rate, the adau1328 can be configured into a dual-line, dac tdm mode, as shown in figure 19 . this mode allows a slower dbclk than normally required by the one-line tdm mode. again, the first four channels of each tdm input belong to the first adau1328 in the chain and the last four channels belong to the second adau1328. the dual-line tdm mode can also be used to send data at a 192 khz sample rate into the adau 1328, as shown in figure 20 . there are two configurations for the adc port to work in daisy-chain mode. the first one is with an abclk at 256 f s shown in figure 21 . the second configuration is shown in figure 22 . note that in the 512 f s abclk mode, the adc channels occupy the first eight slots; the second eight slots are empty. the tdm_in of the first adau1328 must be grounded in all modes of operation. the i/o pins of the serial ports are defined according to the serial mode selected. see tabl e 12 for a detailed description of the function of each pin. see figure 26 for a typical adau1328 configuration with two external stereo dacs and two external stereo adcs. figure 23 through figure 25 show the serial mode formats. for maximum flexibility, the polarity of lrclk and bclk are programmable. in these figures, all of the clocks are shown with their normal polarity. the default mode is i 2 s. dlrclk dbclk 8 dac channels of the first ic in the chain 8 unused slots 8 dac channels of the second ic in the chain msb dsdata1 (tdm_in) o f the second adau1328 dsdata2 (tdm_out) o f the second adau1328 this is the tdm to the first adau1328 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 32 bits dsp second adau1328 first adau1328 06102-054 figure 18. single-line dac tdm daisy-chain mode (applicable to 48 khz sample rate, 16-channel, two adau1328 daisy chain)
adau1328 rev. 0 | page 20 of 32 dlrclk dbclk 8 dac channels of the second ic in the chain 8 dac channels of the first ic in the chain dsdata1 (in) dac l1 dac r1 dac l2 dac r2 dac l1 dac r1 dac l2 dac r2 dsdata3 (in) dac l3 dac r3 dac l4 dac r4 dac l3 dac r3 dac l4 dac r4 dsdata2 (out) dac l1 dac r1 dac l2 dac r2 dsdata4 (out) dac l3 dac r3 dac l4 dac r4 32 bits dsp second adau1328 first adau1328 msb 06102-055 figure 19. dual-line dac tdm mode (applicable to 96 khz sample rate, 16-channel, two adau1328 daisy chain); dsdata3 and dsdata4 are the daisy chain dlrclk dbclk dsdata1 dac l1 dac r1 dac l2 dac r2 dsdata2 dac l3 dac r3 dac l4 dac r4 32 bits msb 06102-058 figure 20. dual-line dac tdm mode (applicable to 192 khz sample rate, 8-channel mode) alrclk abclk asdata2 (tdm_in o f the second adau1328 in the chain) adc l1 adc r1 adc l2 adc r2 4 adc channels of first ic in the chain 4 adc channels of second ic in the chain asdata1 (tdm_out o f the second adau1328 in the chain) adc l1 adc r1 adc l2 adc r2 adc l1 adc r1 adc l2 adc r2 32 bits msb dsp second adau1328 first adau1328 06102-056 figure 21. dual-line adc tdm daisy-chain mode (256 f s abclk, two adau1328 daisy chain)
adau1328 rev. 0 | page 21 of 32 alrclk abclk 4 adc channels of second ic in the chain 4 adc channels of first ic in the chain adc l1 adc r1 adc l2 adc r2 adc l1 adc r1 adc l2 adc r2 asdata1 (tdm_out o f the second adau1328 in the chain) adc l1 adc r1 adc l2 adc r2 asdata2 (tdm_in o f the second adau1328 in the chain) 32 bits msb dsp second adau1328 first adau1328 06102-057 figure 22. dual-line adc tdm daisy-chain mode (512 f s abclk, two adau1328 daisy chain) lrclk bclk sdat a lrclk bclk sdat a lrclk bclk sdat a lsb lsb lsb lsb lsb lsb left channel right channel right channel left channel left channel right channel msb msb msb msb msb msb right-justified mode?select number of bits per channel dsp mode?16 bits to 24 bits per channel i 2 s mode?16 bits to 24 bits per channel left-justified mode?16 bits to 24 bits per channel lrclk bclk sdat a lsb lsb notes 1. dsp mode does not identify channel. 2. lrclk normally operates at f s except for dsp mode, which is 2 f s . 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. msb msb 1/ f s 06102-013 figure 23. stereo serial modes
adau1328 rev. 0 | page 22 of 32 dbclk dlrclk dsdata left-justified mode dsdata right-justified mode dsdata i 2 s-justified mode t dlh t dbh t dbl t dls t dds msb msb msb lsb msb?1 t ddh t dds t ddh t dds t ddh t ddh t dds 06102-014 figure 24. dac serial timing abclk alrclk asdata left-justified mode asdata right-justified mode asdata i 2 s-justified mode t abh lsb msb msb msb msb?1 t abl t als t abdd t abdd t abdd t alh 06102-015 figure 25. adc serial timing
adau1328 rev. 0 | page 23 of 32 table 12. pin function changes in tdm and aux modes (replication of table 11 ) mnemonic stereo modes tdm modes aux modes asdata1 adc1 data out adc tdm data out tdm data out asdata2 adc2 data out adc tdm data in aux data out 1 (to external dac 1) dsdata1 dac1 data in dac tdm data in tdm data in dsdata2 dac2 data in dac tdm data out aux data in 1 (from external adc 1) dsdata3 dac3 data in dac tdm data in 2 (dual- line mode) aux data in 2 (from external adc 2) dsdata4 dac4 data in dac tdm data out 2 (dual- line mode) aux data out 2 (to external dac 2) alrclk adc lrclk in/out adc tdm frame sync in/out tdm frame sync in/out abclk adc bclk in/out adc tdm bclk in/out tdm bclk in/out dlrclk dac lrclk in/out dac tdm frame sync in/out aux lrclk in/out dbclk dac bclk in/out dac tdm bclk in/out aux bclk in/out aux adc 1 lrclk bclk data mclk aux adc 2 lrclk bclk data mclk aux dac 1 aux dac 2 lrclk bclk data mclk lrclk bclk data mclk 30mhz 12.288mhz sharc is running in slave mode (interrupt-driven) sharc adau1328 tdm master aux master fsync-tdm (rfs) rxclk rxdata txclk txdata tfs (nc) asdata2 dsdata4 dbclk dlrclk dsdata2 dsdata3 mclk asdata1 alrclk abclk dsdata1 06102-019 figure 26. example of aux mode connection to shar c? (adau1328 as tdm master/aux master shown)
adau1328 rev. 0 | page 24 of 32 control registers definitions the format is the same for i 2 c and spi ports. the global address for the adau1328 is 0x04, shifted left 1 bit due to the r/ w bit. however, in i 2 c, adr0 and adr1 are ored into bit 17 and bit 8 to provide mult iple chip addressing. all registers are reset to 0, except for the dac volume registers that are set to full volume. note that the first setting in each control register parameter is the default setting. table 13. register format global address r/ w register address data bit 23:17 16 15:8 7:0 table 14. register addresses and functions address function 0 pll and clock control 0 1 pll and clock control 1 2 dac control 0 3 dac control 1 4 dac control 2 5 dac individual channel mutes 6 dac 1l volume control 7 dac 1r volume control 8 dac 2l volume control 9 dac 2r volume control 10 dac 3l volume control 11 dac 3r volume control 12 dac 4l volume control 13 dac 4r volume control 14 adc control 0 15 adc control 1 16 adc control 2 pll and clock control registers table 15. pll and clock control 0 bit value function description 0 0 normal operation pll power-down 1 power-down 2:1 00 input 256 (44.1 khz or 48 khz) mclk pin functionality (pll active) 01 input 384 (44.1 khz or 48 khz) 10 input 512 (44.1 khz or 48 khz) 11 input 768 (44.1 khz or 48 khz) 4:3 00 xtal oscillator enabled mclko pin 01 256 f s vco output 10 512 f s vco output 11 off 6:5 00 mclk pll input 01 dlrclk 10 alrclk 11 reserved 7 0 disable: adc and dac idle internal mclk enable 1 enable: adc and dac active
adau1328 rev. 0 | page 25 of 32 table 16. pll and clock control 1 bit value function description 0 0 pll clock dac clock source select 1 mclk 1 0 pll clock adc clock source select 1 mclk 2 0 enabled on-chip voltage reference 1 disabled 3 0 not locked pll lock indicator (read-only) 1 locked 7:4 0000 reserved dac control registers table 17. dac control 0 bit value function description 0 0 normal power-down 1 power-down 2:1 00 32 khz/44.1 khz/48 khz sample rate 01 64 khz/88.2 khz/96 khz 10 128 khz/176.4 khz/192 khz 11 reserved 5:3 000 1 sdata delay (bclk periods) 001 0 010 8 011 12 100 16 101 reserved 110 reserved 111 reserved 7:6 00 stereo (normal) serial format 01 tdm (daisy chain) 10 dac aux mode (adc-, dac-, tdm-coupled) 11 dual-line tdm table 18. dac control 1 bit value function description 0 0 latch in midcycle (normal) bclk active edge (tdm in) 1 latch in at end of cycle (pipeline) 2:1 00 64 (2 channels) bclks per frame 01 128 (4 channels) 10 256 (8 channels) 11 512 (16 channels) 3 0 left low lrclk polarity 1 left high 4 0 slave lrclk master/slave 1 master 5 0 slave bclk master/slave 1 master 6 0 dbclk pin bclk source 1 internally generated 7 0 normal bclk polarity 1 inverted
adau1328 rev. 0 | page 26 of 32 table 19. dac control 2 bit value function description 0 0 unmute master mute 1 mute 2:1 00 flat de-emphasis (32 khz/44.1 khz/48 khz mode only) 01 48 khz curve 10 44.1 khz curve 11 32 khz curve 4:3 00 24 word width 01 20 10 reserved 11 16 5 0 noninverted dac output polarity 1 inverted 7:6 00 reserved table 20. dac individual channel mutes bit value function description 0 0 unmute dac 1 left mute 1 mute 1 0 unmute dac 1 right mute 1 mute 2 0 unmute dac 2 left mute 1 mute 3 0 unmute dac 2 right mute 1 mute 4 0 unmute dac 3 left mute 1 mute 5 0 unmute dac 3 right mute 1 mute 6 0 unmute dac 4 left mute 1 mute 7 0 unmute dac 4 right mute 1 mute table 21. dac volume controls bit value function description 7:0 0 no attenuation dac volume control 1 to 254 ?3/8 db per step 255 full attenuation
adau1328 rev. 0 | page 27 of 32 adc control registers table 22. adc control 0 bit value function description 0 0 normal power-down 1 power-down 1 0 off high-pass filter 1 on 2 0 unmute adc 1l mute 1 mute 3 0 unmute adc 1r mute 1 mute 4 0 unmute adc 2l mute 1 mute 5 0 unmute adc 2r mute 1 mute 7:6 00 32 khz/44.1 khz/48 khz output sample rate 01 64 khz/88.2 khz/96 khz 10 128 khz/176.4 khz/192 khz 11 reserved table 23. adc control 1 bit value function description 1:0 00 24 word width 01 20 10 reserved 11 16 4:2 000 1 sdata delay (bclk periods) 001 0 010 8 011 12 100 16 101 reserved 110 reserved 111 reserved 6:5 00 stereo serial format 01 tdm (daisy chain) 10 adc aux mode (adc-, dac-, tdm-coupled) 11 reserved 7 0 latch in midcycle (normal) bclk active edge (tdm in) 1 latch in at end of cycle (pipeline)
adau1328 rev. 0 | page 28 of 32 table 24. adc control 2 bit value function description 0 0 50/50 (allows 32-/24-/20-/16-bclk/channel) lrclk format 1 pulse (32-bclk/channel) 1 0 drive out on falling edge (def) bclk polarity 1 drive out on rising edge 2 0 left low lrclk polarity 1 left high 3 0 slave lrclk master/slave 1 master 5:4 00 64 bclks per frame 01 128 10 256 11 512 6 0 slave bclk master/slave 1 master 7 0 abclk pin bclk source 1 internally generated
adau1328 rev. 0 | page 29 of 32 additional modes the adau1328 offers several additional modes for board level design enhancements. to reduce the emi in board level design, serial data can be transmitted without an explicit bclk. see figure 27 for an example of a dac tdm data transmission mode that does not require high speed dbclk. this configuration is applicable when the adau1328 master clock is generated by the pll with the dlrclk as the pll reference frequency. to relax the requirement for the setup time of the adau1328 in cases of high speed tdm data transmission, the adau1328 can latch in the data using the falling edge of dbclk. this effectively dedicates the entire bclk period to the setup time. this mode is useful in cases where the source has a large delay time in the serial data driver. figure 28 shows this pipeline mode of data transmission. both the blck-less and pipeline modes are available on the adc serial data port. dlrclk internal dbclk dsdata dlrclk internal dbclk tdm-dsdata 32 bits 06102-059 figure 27. serial dac data transmission in tdm format without dbclk (applicable only if pll locks to dlrclk. this mode is also available in the adc serial data port) dlrclk dbclk dsdata data must be valid at this bclk edge msb 06102-060 figure 28. i 2 s pipeline mode in dac serial data transmission (applicable in stereo and tdm useful for high frequency tdm transmission. this model is also available in the adc serial data port.)
adau1328 rev. 0 | page 30 of 32 application circuits typical applications circuits are shown in figure 29 through figure 32 . figure 29 shows a typical adc input filter circuit. recommended loop filters for lr clock and master clock as the pll reference are shown in figure 30 . output filters for the dac outputs are shown in figure 31 and figure 32 for the noninverting and inverting cases, respectively. 2 1 3 op275 ? + 6 7 5 op275 ? + 5.76k ? 5.76k ? 237 ? 5.76k ? 120pf 600z a udio input 100pf 5.76k ? 120pf 4.7f + 237 ? 4.7f + 100pf 1nf npo 1nf npo adcxn adcxp 06102-023 figure 29. typical adc input filter circuit 39nf + 2.2nf lf lrclk a vdd2 3.32k ? 5.6nf 390nf lf mclk avdd2 562 ? 0 6102-027 figure 30. recommended loop filters for lrclk or mclk pll reference 3 1 2 op275 + ? 4.75k ? 4.75k ? 4.7f + dac out 240p f npo 270pf npo 3.3nf npo audio output 4.99k ? 604 ? 4.99k ? 49.9k ? 06102-024 figure 31. typical dac output filter circuit (single-ended, noninverting) 2 1 3 op275 ? + 3.01k ? 11k ? 4.7f + dac out cm 0.1f 270pf npo 68pf npo 2.2nf npo audio output 604 ? 49.9k ? 11k? 06102-025 figure 32. typical dac output filter circuit (single-ended, inverting)
adau1328 rev. 0 | page 31 of 32 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 33. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model temperature range package description package option adau1328bstz 1 ?40c to +85c 48-lead lqfp st-48 ADAU1328BSTZ-RL 1 ?40c to +85c 48-lead lqfp, 13 reel st-48 eval-adau1328eb evaluation board 1 z = pb-free part.
adau1328 rev. 0 | page 32 of 32 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d061 02-0-6/06(0)

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